1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having a first semiconductor device and a second semiconductor device capable of being SEPP connected, the first semiconductor device including an NPN power transistor formed on a first semiconductor substrate and the second semiconductor device including a PNP power transistor complementary to the NPN power transistor formed on a second semiconductor substrate.
2. Description of the Related Art
An output or final stage of a power amplifier uses a complementary pair of NPN and PNP power transistors SEPP (single ended push-pull) connected to output a large power. An SEPP circuit has a bias circuit for applying a bias voltage between the bases of the two power transistors. This bias voltage is set to generally the same as the total forward voltage drop between the bases and emitters of the two power transistors. Therefore, an idling current (e.g., about several tens mA for a B-class amplifier having a maximum output of several tens W) flows through the two power transistors to prevent crossover distortions of an output waveform.
The forward voltage drop V.sub.BE between the base and emitter of a power transistor has a negative temperature coefficient of about -2 to -2.5 mV/.degree. C. If the bias voltage V.sub.bias is maintained constant, the operating point changes as the temperature rises by heat generated by the power transistor, so that the idling current increases which causes heat generation and temperature risk. This vicious cycle (thermorunaway) may break both the power transistors. In order to avoid this, bias circuits shown in FIGS. 13 and 14 have been used. The bias circuit 1 shown in FIG. 13 is of a diode type constituted of serially connected n diodes D.sub.1 to D.sub.n and a variable resistor VR.sub.1 for adjusting a bias voltage (idling current). The bias circuit 3 shown in FIG. 14 is of a transistor type constituted of a bias transistor 2, a fixed resistor R.sub.11, a variable resistor VR.sub.2, and a fixed resistor R.sub.12. The diodes D.sub.1 to D.sub.n and bias transistor 2 are thermally coupled to NPN and PNP power transistors 4 and 5 to effect temperature compensation of the idling current. Since the forward voltage drop V.sub.F1 to V.sub.Fn has the same negative temperature coefficient of about -2 to -2.5 mV/.degree. C., the bias voltage V.sub.bias lowers as the temperature rises, so that the idling current can be maintained constant. Furthermore, since the forward voltage drop V.sub.BE between the base and emitter of the bias transistor 2 has the same negative temperature coefficient of about -2 to -2.5 mV/.degree. C., the bias voltage lowers as the temperature rises, so that the idling current can be maintained constant.
In FIGS. 13 and 14, reference numerals 6 and 7 represent emitter resistors. The final driver stage 10 is constituted of a resistor R5, a transistor Tr5, a resistor R6, and a transistor Tr6. The drive stage 10 is connected via oscillation suppressing resistors R7 and R8 to the bias circuit 1, 3.
NPN and PNP power transistors are available in markets as discrete semiconductor devices. If NPN and PNP power transistors are SEPP connected as the final stage of a power amplifier, NPN and PNP power transistors having desired electrical characteristics are selected and fixed to a heat sink. Diodes and transistors for bias circuits are also available in markets as discrete semiconductor devices having various types of electrical characteristics. Diodes and transistors having electrical characteristics suitable for bias circuits are selected and fixed to the same heat sink as that of the power transistors to thermally couple them to the power transistors.
FIG. 15 shows an example of a wiring layout of the driver and final stages of the power amplifier using the transistor type bias circuit 3 shown in FIG. 14. Reference numeral 8 represents a heat sink, reference numeral 9 represents a printed circuit board, and reference numerals 4 and 5 represent NPN and PNP power transistors fixed to the heat sink 8, the base terminals (B) and (B'), collector terminal (C) and (C'), and emitter terminals (E) and (E') of the NPN and PNP power transistors being connected to the printed board circuit 9. The NPN and PNP power transistors each are constituted of Darlington connected transistors. Reference numerals 6 and 7 represent emitter resistors. Reference numeral 2 represents a bias transistor fixed to the heat sink 8, the base terminal (B), collector terminal (C), and emitter terminal (E) of the bias transistor being connected to the printed circuit board 9. The bias transistor 2 constitutes a bias circuit in combination with a fixed resistor R.sub.11, a variable resistor VR.sub.2, and a fixed resistor R.sub.12.
As seen from FIG. 15, since the bias transistor 2 and NPN and PNP power transistors 4 and 5 are discrete components, all of them are required to be fixed separately to the heat sink 8. Much works are therefore necessary resulting in high cost. Since the bias transistor 2 is physically remote from the base-emitter junctions of the two NPN and PNP power transistors 4 and 5, the temperature rise of the NPN and PNP power transistors 4 and 5 has a time lag until it is transmitted to the bias transistor 2. Furthermore, since the bias transistor 2 is difficult to raise its temperature to the temperatures of the NPN and PNP power transistors 4 and 5, reliable temperature compensation for the idling current is difficult and so the reliability of preventing thermorunaway is low.
Still further, since the bias transistor 2 is disposed between the NPN and PNP power transistors 4 and 5 and interconnections are made on the printed circuit board 9, the interconnections between the collector terminals (C) and (C') and emitter terminals (E) and (E') become long. Therefore, a large mount area is required, a large electromagnetic radiation is generated because of inductance of printed wires, and output distortion becomes large.
These disadvantages are also true for the diode type bias circuit.
Several semiconductor devices with ideal thermal coupling have been proposed in which an NPN or PNP power transistor and a temperature compensating and biasing circuit diode are integrally formed on the same semiconductor substrate (Japanese Patent Laid-open Publications Nos. 53-29082, 63-169764, 63-190381, and so on). Use of these semiconductor devices for an SEPP circuit may eliminate the above disadvantages.
In order to form a diode on the same semiconductor substrate as an NPN power transistor at as small cost as possible, a PN junction diode is used. However, if the device structure is made simple, parasitic transistors are inevitably formed. It is possible to use the base-emitter junction of a parasitic transistor as a diode. However, in this case, it is necessary to lower the current amplification factor h.sub.fe of the parasitic transistor as small as 1/10 or lower. The forward voltage drop of the diode at this amplification factor is about 1 V which is very different from the forward voltage drop V.sub.BE .apprxeq.0.6 V between the base-emitter of a power transistor (if the power transistor is constituted of two-stage Darlington connected transistors, 2V.sub.BE .apprxeq.1.2 V, and for three-stage Darlington connected transistors, 3V.sub.BE .apprxeq.1.8 V).
Similar to the above, if a PN junction diode is formed on the same semiconductor substrate as a PNP power transistor, the forward voltage drop of the diode becomes very different from the forward voltage drop V.sub.BE .apprxeq.0.6 V between the base-emitter of a power transistor (if the power transistor is constituted of two-stage Darlington connected transistors, 2V.sub.BE .apprxeq.1.2 V, and for three-stage Darlington connected transistors, 3V.sub.BE .apprxeq.1.8 V).
Therefore, even if a first semiconductor device integrating an NPN power transistor and a temperature compensating and biasing diode on the same semiconductor substrate is used in combination with a second semiconductor device integrating a PNP power transistor and a temperature compensating and biasing diode on the same semiconductor substrate, the bias voltages mismatch. Therefore, this combination cannot be applied and semiconductor makers do not manufacture and sell such semiconductor devices.
As shown in FIG. 3 of Japanese Patent Laid-open Publication No. 63-169764, if a power transistor and a diode are formed on different semiconductor substrates, the forward voltage drop of the diode can be set about 0.6 V same as the forward voltage drop between the base and emitter of the power transistor. However, thermal coupling becomes imperfect and the manufacture cost rises.
From this reason, with the conventional techniques, NPN and PNP power transistors and bias circuit transistors or diodes are prepared independently and mounted separately on a heat sink. Therefore, the problems described earlier cannot be solved, the problems including complicated works in manufacturing SEPP circuits, poor temperature compensation, large mount area, and large output distortion.